Ioannis Sourdis
Visar 69 publikationer
MEMPLEX: A Multi-Chiplet NUMA Architecture with Data Replication and Migration
A Performance Analysis of Chiplet-Based Systems
A Parallel Hash Table for Streaming Applications
BZSim: Fast, Large-Scale Microarchitectural Simulation with Detailed Interconnect Modeling
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
Stream Aggregation with Compressed Sliding Windows
L2C: Combining Lossy and Lossless Compression on Memory and I/O
FlatPack: Flexible Compaction of Compressed Memory
FastTrackNoC: A NoC with FastTrack Router Datapaths
Streamzip: Compressed Sliding-Windows for Stream Aggregation
Reliability Analysis of Compressed CNNs
Introduction to the Special Section on FPL 2019
A Specialized Memory Hierarchy for Stream Aggregation
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers
MemSZ: Squeezing Memory Traffic with Lossy Compression
Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
Mapping Multiple LSTM models on FPGAs
AVR: Reducing Memory Traffic with Approximate Value Reconstruction
Time-SWAD: A dataflow engine for time-based single window stream aggregation
Energy-efficient Runtime Management of Heterogeneous Multicores using Online Projection
LLC-guided data migration in hybrid memory systems
Decoupled fused cache: Fusing a decoupled LLC with a DRAM cache
DDRNoC: Dual Data-Rate Network-on-Chip
COSSIM: An open-source integrated solution to address the simulator gap for systems of systems
FreewayNoC: A DDR NoC with Pipeline Bypassing
Attacks on Heartbeat-Based Security Using Remote Photoplethysmography
FusionCache: Using LLC tags for DRAM cache
Enhancing heart-beat-based security for mHealth applications
BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations
Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures
Towards real-time whisker tracking in rodents for studying sensorimotor disorders
Odd-ECC: On-demand DRAM error correcting codes
DDRNoC: Dual Data-Rate Network-on-Chip
SWAS: Stealing Work Using Approximate System-Load Information
Single Window Stream Aggregation using Reconfigurable Hardware
Performance Analysis of Accelerated Biophysically-Meaningful Neuron Simulations
RQNoC: A resilient quality-of-service network-on-chip with service redirection
Runtime Management of Adaptive MPSoCs for Graceful Degradation
Resilient chip multiprocessors with mixed-grained reconfigurability
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems
Secure key-exchange protocol for implants using heartbeats
Increasing the Trustworthiness of Embedded Applications
On using a von neumann extractor in heart-beat-based security
Reducing the performance overhead of resilient CMPs with substitutable resources
Secure hardware-software architectures for robust computing systems
A Probabilistic Analysis of Resilient Reconfigurable Designs
Real-time olivary neuron simulations on dataflow computing machines
FPGA-based biophysically-meaningful modeling of olivocerebellar neurons
Adaptive entity-identifier generation for IMD emergency access
Design and analysis of binary tree static random access memory for low power embedded systems
Peak misdetection in heart-beat-based security: Characterization and tolerance
The DeSyRe runtime support for fault-tolerant embedded MPSoCs
A dependable coarse-grain reconfigurable multicore array
A runtime manager for gracefully degrading SoCs
DeSyRe: On-demand adaptive and reconfigurable fault-tolerant SoCs
A System Architecture, Processor, and Communication Protocol for Secure Implants
on-Demand System Reliability: The DeSyRe project
Software modification aided transient error tolerance for embedded systems
DeSyRe: On-demand system reliability
Guest editorial: Workshop on Reconfigurable Computing
Heuristic Search for Adaptive, Defect-Tolerant Multiprocessor Arrays
The DeSyRe Project: On-Demand System Reliability
Communication Service for hardware tasks executed on dynamic and partial reconfigurable resource
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
HiPEAC: Upcoming Challenges in Reconfigurable Computing
Longest prefix match and updates in range tries
Reconfigurable Acceleration and Dynamic Partial Self-Reconfiguration in General Purpose Computing
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Visar 2 forskningsprojekt
Green Computing Node for European micro-servers (EUROSERVER)