Per Stenström
Showing 195 publications
DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators
HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
SCALE: Secure and Scalable Cache Partitioning
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
Bounding the execution time of parallel applications on unrelated multiprocessors
GBDI: Going Beyond Base-Delta-Immediate Compression with Global Bases
Federated Scheduling of Sporadic DAGs on Unrelated Multiprocessors
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling
A GPU Register File using Static Data Compression
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
SaC: Exploiting execution-time slack to save energy in heterogeneous multicore systems
SimICS/sun4m: A virtual workstation
QoS-driven coordinated management of resources to save energy in multi-core systems
Trends on heterogeneous and innovative hardware and software systems
Scheduling parallel real-time recurrent tasks on multicore platforms
ProFess: A Probabilistic Hybrid Main Memory Management Framework for High Performance and Fairness
Global dead-block management for task-parallel programs
Timing-anomaly free dynamic scheduling of task-based parallel applications
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures
Rock: A framework for pruning the design space of hybrid main memory systems
Runtime-Assisted Global Cache Management for Task-based Parallel Programs
PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor
Timing-anomaly free dynamic scheduling of task-based parallel applications
RADAR: Run-time assisted Dead-Region Management for Last-Level Caches
ProF: Probabilistic Hybrid Main Memory Management for High Performance and Fairness
EUROSERVER: Share-anything scale-out micro-server design
A Case for Runtime-Assisted Global Cache Management
Adaptive row addressing for cost-efficient parallel memory protocols in large-capacity memories
RADAR: Runtime-assisted dead region management for last-level caches
Enhancing Garbage Collection Synchronization using Explicit Bit Barriers
Performance Impact of Batching Web Application Requests using Hot-spot Processing on GPUs
HyComp: A Hybrid Cache Compression Method for Selection of Data-Type-Specific Compression Methods
RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches
A Case for a Value-Aware Cache
Effective Resource Management Towards Efficient Computing
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory
Characterizing and Exploiting Small-Value Memory Instructions
Temporal Partitioning on Multicore Platform
Proceedings of the 2014 ACM International Conference on Supercomputing
Removal of Conflicts in Hardware Transactional Memory Systems
Overhead-Aware Temporal Partitioning on Multicore Processors
SC2: A statistical compression cache scheme
Crystal: A design-time resource partitioning method for hybrid main memory
Runtime-guided cache coherence optimizations in multi-core architectures
A Design-Time Resource Partitioning Method for Hybrid Main Memory
Introduction to the JPDC special issue on Perspectives on Parallel and Distributed Processing
Performance and energy analysis of the restricted transactional memory implementation on haswell
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures
Moving from Petaflops to Petadata
Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory
Towards automatic resource management in parallel architectures.
HARP: Adaptive Abort Recurrence Prediction for Hardware Transactional Memory
Transactions on Architectures and Code Optimizations
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transaction Memory
A Data Forwarding Scheme for Task-based Programming Models
Critical lock analysis: Diagnosing critical section bottlenecks in multithreaded applications
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory
Transactional prefetching: Narrowing the window of contention in hardware transactional memory
ZEBRA: A data-centric, hybrid-policy hardware transactional memory design
Eager meets lazy: The impact of write-buffering on hardware transactional memory
The Impact of Non-coherent on Lazy HardwareTransactional Memory Systems
A Unified Approach to Eliminate Memory Accesses Early
Diagnosing Critical Section Bottlenecks in Multithreaded Applications
Transactions on High-Performance Embedded Architectures and Compilers Vol 3
Coherence-Less Model for Shared-Memory, Speculative Multi-core Processors
Implications of Merging Phases on Scalability of Multi-core Architectures
Classification and Elimination of Conflicts in Hardware-Transactional Memory Systems
Implications of Merging Phases on Scalability of Multicore Architectures
The impact of non-coherent buffers on lazy hardware transactional memory systems
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory
Techniques for Reduction of Conflicts in Hardware Transactional Memory.
Transaction on Architectures and Code Optimization
Hints Based Speculative Execution for Exploiting Probabilistic Parallel Execution.
Transactions on High Performance and Embedded Architectures and Compilers - Vol 4
Generating and Comparing Memory Access Ranges for Speculative Throughput Computing
Characterization and Exploitation of Silent Loads
The VELOX Transactional Memory Stack
Diagnosing Serialization Bottlenecks in Multi-threaded Applications on Multi-core Processors
Sematic based speculative parallel execution.
Simple Performance Optimization Techniques for Hardware Transactional Memory Systems
Semantic Information Driven Speculative Execution
Characterization and Exploitation of Narrow-Width Loads:The Narrow-Width Cache Approach
LV*: A Class of Lazy-Versioning HTMs for Low-Cost Integration of Transactional Memory Systems
LV*: A Low Complexity Lazy Versioning HTM Infrastructure
Schemes for avoiding starvation in transactional memory systems
Semantic information driven speculative execution
Transactions on High-Performance Embedded Architectures and Compilers
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
A Flexible Code-Compression Scheme using Partitioned Look-Up Tables
Cancellation of Loads that Return Zero Using Zero-Value Caches
Zero-Value Caches: Cancelling Loads that Return Zero.
Using Hoarding to Increase the Availability in Shared File Systems
Zero-Value Caches: Cancelling Loads that Return Zero
Early Detection and Bypassing of Trivial Operations to Improve Energy Efficiency of Processors
Reducing Roll-back Overhead in Transactional Memory Systems by Checkpointing Conflicting Accesses
Leveraging data promotion for low power D-NUCA caches
Zero Loads: Canceling Load Requests by Tracking Zero Values
The worst-case execution-time problem - overview of methods and survey of tools
Accommodation of the Bandwidth of Large Cache Blocks using Cache/Memory Link Compression
A Micro-Architectural Power-Saving Technique for D-NUCA Caches
Proceedings of the 14th IEEE Symp. on High-Performance Computer Architecture
Simple Penalty-Sensitive Cache Replacement Policies
A Flexible Code Compression Scheme using Partitioned Look-Up Tables
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems
Memory Link Compression Schemes: A Value Locality Perspective
Proceedings of the 2007 ACM International Conference on Computing Frontiers
Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.
SimWattch: Integrating complete-system and user-level performance and power simulators
Effectiveness of Caching in a Distributed Digital Library.
An Adaptive Shared/Private NUCA Cache Partiotioning Scheme for Chip Multiprocessors
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems
Exposed Datapath for Efficient Computing
The Paradigm Shift to Multi-Cores: Opportunities and Challenges
Improving Power Efficiency of D-NUCA Caches
Characterization of Apache web server with Specweb2005
Proceedings of the 2007 International Conference on HiPEAC
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
Starvation-Free Transactional Memory System Protocols.
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
Limits on Thread-Level Speculative Parallelism in Embedded Applications
Implicit Transactional Memory in Kilo-Instruction Processors
Loop-Level Speculative Parallelism in Embedded Applications.
Two Threads in the Machine is Better than Eight in the Bush
High-Performance Embedded Architecture and Compilation Roadmap
Enhancing Lower Level Cache Performance by Early Miss Determination and Bypassing.
Exposed Datapath for Efficient Computing
Starvation-Free Commit Arbitration Policies for Transactional Memory Systems.
A Cache-Partition Aware Replacement Policy for Chip Multiprocessors.
Exploitation of Value Locality for Memory Link Compression
Penalty-Sensitive Replacement Policies for Caches.
A Cache Replacement Algorithm based on Frequency and Recency for Chip Multiprocessors.
Value-Cache Based Compression Schemes for Multiprocessors
Reducing Misspeculation Overhead for Module-Level Speculative Execution
Implementing Kilo-Instruction Multiprocessors
Enhancing Simulation Speed using Matched-Pair Comparison
A Cost-Effective Memory Organization for Future Servers
Keynote 2: The chip-multiprocessing paradigm shift: Opportunities and challenges
Evaluation of Extended Dictionary-Based Static Code Compression Techniques
Self-Correcting LRU Replacement Policies.
A Cache Block Reuse Prediction Scheme
Coherence Predictor Cache: A Resource Efficient Coherence Message Prediction Infrastructure.
SimWattch: An Approach to Integrate Complete-System with User-Level Performance/Power Simulators
An Evaluation of Document Prefetching in a Distributed Digital Library
A Novel Approach to Cache Block Reuse Prediction
An Evaluation of Document Prefetching in a Distributed Digital Library
Improving Speculative Thread-Level Parallelism Through Module Run-Length Prediction
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
FlexSoC: Combining Flexibility and Efficiency in SoC Designs
Speculative Lock Reordering: Optimistic Out-of-Order Execution of Critical Sections
Evaluation of Document Prefetching in a Distributed Digital Library.
Reducing Misspeculation Overhead for Module-Level Speculative Execution
TLB and Snoop Energy-Reduction using Virtual Caches for Low-Power Chip-Multiprocessors
Improvement of energy-efficiency in off-chip caches by selective prefetching
An All-Software Thread-Level Data Dependence Speculation System for Multiprocessors
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of a Conditional Branch
Download publication list
You can download this list to your computer.
Filter and download publication list
As logged in user (Chalmers employee) you find more export functions in MyResearch.
You may also import these directly to Zotero or Mendeley by using a browser plugin. These are found herer:
Zotero Connector
Mendeley Web Importer
The service SwePub offers export of contents from Research in other formats, such as Harvard and Oxford in .RIS, BibTex and RefWorks format.
Showing 20 research projects
classIC - Chalmers Lund Center for Advanced Semiconductor System Design
Pilot using Independent Local & Open Technologies (The European PILOT)
Principer för beräknande minnesenheter (PRIDE)
eProcessor: European, extendable, energy- efficient, extreme-scale, extensible, Processor Ecosystem
PRIME: Principled Designs of Processing-in-Memory Parallel Systems
High Performance Embedded Architecture and Compilation
The European Processor Initiative (EPI)
High Performance and Embedded Architecture and Compilation (HiPEAC5)
TEchnology TRAnsfer via Multinational Application eXperiments (TETRAMAX)
High Performance and Embedded Architecture and Compilation (HiPEAC4)
ACE: Approximate Algorithms and Computing Systems
Meeting Challenges in Computer Architecture (MECCA)
Green Computing Node for European micro-servers (EUROSERVER)
A Framework for Fine-Grain Resource Management in Heterogeneous Parallel Architectures
High Performance and Embedded Architecture and Compilation (HiPEAC)