Vertically stacked carbon nanotube-based interconnects for through silicon via application
Journal article, 2015
Stacking of silicon chips with carbon nanotube (CNT)-based through-silicon vias (TSVs) is experimentally demonstrated. Polymer filling is used to improve the transfer quality of CNTs into pre-etched silicon holes. Special hexagonal CNTs are designed to achieve high aspect ratio (10:1) CNT vias. TSVs filled with closely packed CNTs show a highly linear dc I - V response. The proposed process works at room temperature, which makes it compatible with existing device fabrication flow.
Carbon nanotube (CNT)
interconnect
through-silicon via (TSV)
3D stacking
transfer
densification
Author
Di Jiang
Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems Laboratory
Wei Mu
Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems Laboratory
Si Chen
Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems Laboratory
Yifeng Fu
SHT Smart High Tech AB
Kjell Jeppson
Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems Laboratory
Johan Liu
Chalmers, Microtechnology and Nanoscience (MC2), Electronics Material and Systems Laboratory
IEEE Electron Device Letters
0741-3106 (ISSN)
Vol. 36 5 499-501Carbon Based Smart Systems for Wireless Applications (NANO RF)
European Commission (FP7) (EC/FP7/318352), 2012-09-01 -- 2015-08-31.
Areas of Advance
Nanoscience and Nanotechnology
Production
Subject Categories (SSIF 2011)
Electrical Engineering, Electronic Engineering, Information Engineering
Nano Technology
Infrastructure
Nanofabrication Laboratory
DOI
10.1109/LED.2015.2415198