A highly efficient 1-GHz, 15-W power amplifier design based on a 50-V LDMOS transistor

Paper i proceeding, 2010

We present a 15-W, I-GHz harmonically tuned power amplifier (PA) with a power added efficiency (PAE) of 75%. The PA design is based on a packaged 50-V Si-LDMOS engineering sample. The PAE is maximized by an appropriate tuning of the fundamental and second harmonics, while the higher harmonics are shortened by the parasitic drain-source capacitance. The PA design is based on a simplified transistor model which is optimized for harmonically tuned PAs. The model parameters are extracted from IV- and S-parameter measurements of the packaged LDMOS device. A good agrement between the simulation and measurement results shows the accuracy of the modeling and PA design procedure. © 2010 IEEE.