Design considerations and laboratory testing of power circuits for parallel operation of silicon carbide MOSFETs

Paper in proceeding, 2015

In this paper, the impact of using parallel SiC MOSFETs as the switching device is investigated. Measurement considerations for a double pulse test are discussed, and the influence of the load inductor characteristic and the voltage measurement technique on the measurement results is demonstrated. It is shown that the inductor load can produce high frequency oscillations of up to 10 % of the load current in the switching current, which can wrongly be associated with the switching device. It is also shown that the standard earth connection of passive voltage probes can induce an extra stray inductance in the measurement loop, which can lead to a measurement of an extra overvoltage of up to 50 V, which is not due to the actual switching. Moreover, the dependency of turn-on and turn-off losses on the load current and the dc-link voltage is presented. It is shown that doubling the load current would increase the switching losses more than the double amount. Therefore, use of two parallel MOSFETs instead of a single one would decrease the total switching losses for a given load current. On the other hand, the parallel configuration is shown to have a higher overvoltage than one single MOSFET for a similar load current. This, however, can be reduced by a higher gate resistance which will eventually keep the total switching loss of parallel configuration equal to the single MOSFET configuration for a given load current. Finally, it is also shown that switching losses can be greatly decreased by decreasing the gate resistance, but this leads to a higher overvoltage on the device. Therefore, the final choice for design is a compromise between the switching losses and the overvoltage.