Effective reconfigurable design: The FASTER approach
Paper in proceeding, 2014
While fine-grain, reconfigurable devices have been available for years, they are mostly used in a fixed functionality, "asic-replacement" manner. To exploit opportunities for flexible and adaptable run-time exploitation of fine grain reconfigurable resources (as implemented currently in dynamic, partial reconfiguration), better tool support is needed. The FASTER project aims to provide a methodology and a tool-chain that will enable designers to efficiently implement a reconfigurable system on a platform combining software and reconfigurable resources. Starting from a high-level application description and a target platform, our tools analyse the application, evaluate reconfiguration options, and implement the designer choices on underlying vendor tools. In addition, FASTER addresses micro-reconfiguration, verification, and the run-time management of system resources. We use industrial applications to demonstrate the effectiveness of the proposed framework and identify new opportunities for reconfigurable technologies.
Author
Dionisios N. Pnevmatikatos
Foundation for Research and Technology-Hellas
T. Becker
Imperial College London
A. Brokalakis
Georgi Gaydadjiev
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
W. Luk
Imperial College London
Kyprianos D. Papadimitriou
Foundation for Research and Technology-Hellas
Ioannis Papaefstathiou
D. Pau
STMicroelectronics
O. Pell
Maxeler Technologies
Christian Pilato
Politecnico di Milano
M. D. Santambrogio
Politecnico di Milano
Donatella Sciuto
Politecnico di Milano
D. Stroobandt
Universiteit Gent
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
03029743 (ISSN) 16113349 (eISSN)
Vol. 8405 318-3239783319059594 (ISBN)
Subject Categories (SSIF 2011)
Computer and Information Science
DOI
10.1007/978-3-319-05960-0-35
ISBN
9783319059594