Methodology for Power-Aware Coherent Receiver Design
Paper in proceeding, 2013
We describe a methodology to design and evaluate DSP hardware for a coherent receiver. Important parameters that can be assessed include DSP power consumption and chip area.
Author
Tauseef Ahmad
Chalmers, Computer Science and Engineering (Chalmers)
Yun Ai
Chalmers, Signals and Systems
Pavithra Muralidharan
Chalmers, Computer Science and Engineering (Chalmers)
Naga Vishnukanth Irukulapati
Chalmers, Signals and Systems, Kommunikationssystem, informationsteori och antenner
Pontus Johannisson
Chalmers, Microtechnology and Nanoscience (MC2), Photonics
Henk Wymeersch
Chalmers, Signals and Systems, Kommunikationssystem, informationsteori och antenner
Erik Agrell
Chalmers, Signals and Systems, Kommunikationssystem, informationsteori och antenner
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Magnus Karlsson
Chalmers, Microtechnology and Nanoscience (MC2), Photonics
Optics InfoBase Conference Papers
21622701 (eISSN)
SPT4D.4-9781557529817 (ISBN)
Areas of Advance
Information and Communication Technology
Subject Categories (SSIF 2011)
Telecommunications
Communication Systems
DOI
10.1364/SPPCOM.2013.SPT4D.4
ISBN
9781557529817