FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration
Paper in proceeding, 2012
The FASTER project aims to ease the definition, implementation and use of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving better performance and extending product functionality and lifetime via the addition of new features that work at hardware speed. This is a clear advantage over the more straightforward software component adaptivity. However, designing a changing hardware system is both challenging and time consuming. The FASTER project will facilitate the use of reconfigurable technology by providing a complete methodology that enables designers to easily specify, analyse, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. To better adapt to different application requirements, the tool-chain will support both region-based and micro-reconfiguration and provide a flexible run-time system that will efficiently manage the reconfigurable resources. We will use applications from the embedded, high performance computing, and desktop domains to demonstrate the potential benefits of the FASTER tools on metrics such as performance, power consumption and total ownership cost.
reconfigurable computing
relocation
partial reconfiguration
tools for reconfiguration
run-time reconfiguration
run-time system
Author
Dionisios N. Pnevmatikatos
Foundation for Research and Technology-Hellas
T. Becker
Imperial College London
A. Brokalakis
K. Bruneel
Universiteit Gent
Georgi Gaydadjiev
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
W. Luk
Imperial College London
Kyprianos D. Papadimitriou
Foundation for Research and Technology-Hellas
Ioannis Papaefstathiou
O. Pell
Maxeler Technologies
Christian Pilato
Politecnico di Milano
M. Robart
STMicroelectronics
M. D. Santambrogio
Politecnico di Milano
Donatella Sciuto
Politecnico di Milano
D. Stroobandt
Universiteit Gent
T. Todman
Imperial College London
15th Euromicro Conference on Digital System Design, DSD 2012; Cesme, Izmir; Turkey; 5 September 2012 through 8 September 2012
234-241 6386896
978-076954798-5 (ISBN)
Facilitating Analysis and Synthesis Technologies\nfor Effective Reconfiguration (FASTER)
European Commission (FP7) (EC/FP7/287804), 2011-09-01 -- 2014-11-30.
Subject Categories (SSIF 2011)
Computer and Information Science
DOI
10.1109/DSD.2012.59
ISBN
978-076954798-5