Design principles for synthesizable processor cores
Paper in proceeding, 2012
As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
synthesizable processor core
FPGA architectures
Pipe linings
Benchmarking
Embedded computing
Embedded software
Field programmable gate arrays (FPGA)
Processor architectures
predication
System clock
Architecture
FPGA implementations
Design Principles
FPGA
Processor cores
Pipeline processing systems
Pipeline stall
Computer architecture
pipelining
Author
P. Schleuniger
Danmarks Tekniske Universitet
Sally A McKee
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
S. Karlsson
Danmarks Tekniske Universitet
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
03029743 (ISSN) 16113349 (eISSN)
Vol. 7179 111-122978-364228292-8 (ISBN)
Subject Categories (SSIF 2011)
Computer and Information Science
DOI
10.1007/978-3-642-28293-5_10
ISBN
978-364228292-8